Multilayer ceramic capacitor

ABSTRACT

A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application No. 2019-009747 filed Jan. 23, 2019. The entire contents of this application are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a multilayer ceramic capacitor.

2. Description of the Related Art

In recent years, electronic devices, such as mobile telephones and mobile music players, have been reduced in size and thickness. The electronic devices have multiple multilayer ceramic electronic components embedded in or mounted on substrates, and the multilayer ceramic electronic components also have been reduced in size and thickness in association with the reduction in size of electronic devices. With a reduction in thickness of multilayer ceramic capacitors, how to secure the strength of the multilayer ceramic capacitors has been an issue.

As a multilayer ceramic electronic component having an improved chip strength, a multilayer ceramic capacitor to be embedded in a substrate as described in Japanese Patent Laid-Open No. 2015-65394 was proposed. The multilayer ceramic capacitor includes external electrodes having band surfaces with a predetermined length or longer, so that the external electrodes can connect to external interconnections through via holes. At the same time, the external electrodes have a reduced thickness so as to increase the ceramic body thickness in the entire chip thickness, thereby preventing cracks or other damage.

The multilayer ceramic capacitor described in Japanese Patent Laid-Open No. 2015-65394 is 300 μm in thickness in the stacking direction. However, in association with the recent further reduction in size and thickness of electronic devices, multilayer ceramic capacitors are required to be further reduced in thickness. For a multilayer ceramic capacitor having such a reduced thickness, external electrodes may be formed by plating deposition through a metallic medium onto leading portions of internal electrodes. However, the thickness reduction significantly decreases the likelihood that the medium will come into contact with the leading portions. This makes the plating precipitation onto the lateral surfaces difficult.

SUMMARY OF THE INVENTION

Preferred embodiments of the present invention provide multilayer ceramic capacitors each having a reduced thickness and including external electrodes reliably provided thereon by plating deposition.

A multilayer ceramic capacitor according to a preferred embodiment of the present invention includes a stacked body and a plurality of external electrodes. The stacked body includes a plurality of dielectric layers and a plurality of internal electrodes which are stacked. The stacked body includes a first main surface and a second main surface opposite to each other in a stacking direction, a first lateral surface and a second lateral surface opposite to each other in a longitudinal direction orthogonal or substantially orthogonal the stacking direction, and a third lateral surface and a fourth lateral surface opposite to each other in a width direction orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction. The plurality of external electrodes are disposed on the lateral surfaces of the stacked body. The plurality of internal electrodes include a plurality of first internal electrodes and a plurality of second internal electrodes alternately stacked, with the dielectric layers being interposed therebetween. The first internal electrodes include first leading portions extending to the first and third lateral surfaces, and second leading portions extending to the second and fourth lateral surfaces. The second internal electrodes include third leading portions extending to the first and fourth lateral surfaces, and fourth leading portions extending to the second and third lateral surfaces. The plurality of external electrodes include first, second, third, and fourth external electrodes. The first external electrode is connected to the first leading portions by covering the first leading portions exposed at the first and third lateral surfaces. The first external electrode covers a portion of each of the first main surface, the second main surface, the first lateral surface, and the third lateral surface. The second external electrode is connected to the second leading portions by covering the second leading portions exposed at the second and fourth lateral surfaces. The second external electrode covers a portion of each of the first main surface, the second main surface, the second lateral surface, and the fourth lateral surface. The third external electrode is connected to the third leading portions by covering the third leading portions exposed at the first and fourth lateral surfaces. The third external electrode covers a portion of each of the first main surface, the second main surface, the first lateral surface, and the fourth lateral surface. The fourth external electrode is connected to the fourth leading portions by covering the fourth leading portions exposed at the second and third lateral surfaces. The fourth external electrode covers a portion of each of the first main surface, the second main surface, the second lateral surface, and the third lateral surface. A relationship of about 0.85≤W/L≤about 1, and L≤about 750 μm, are satisfied, where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction. The dielectric layers include outer layer portions and an effective layer portion. One of the outer layer portions is located adjacent to the first main surface of the stacked body, and the other of the outer layer portions is located adjacent to the second main surface of the stacked body. The one of the outer layer portions is one of the dielectric layers that is located between the first main surface and one of the internal electrodes that is closest to the first main surface. The other of the outer layer portions is one of the dielectric layers that is located between the second main surface and one of the internal electrodes that is closest to the second main surface. The effective layer portion is a region sandwiched between the outer layer portions. Where a dimension of the stacked body in the stacking direction is denoted by t, and a dimension of the effective layer portion in the stacking direction is denoted by t′, a ratio of the dimension t′ of the effective layer portion in the stacking direction to the dimension t of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.

The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an outside perspective view showing an example multilayer ceramic capacitor according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 5 is an exploded perspective view of the stacked body shown in FIGS. 1 to 4 .

FIG. 6 is a plan view of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 7 is a front view of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 8 is a right side view of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 9 is an enlarged cross-sectional view showing an external electrode in the cross-sectional view of FIG. 2 or 3 in enlarged view.

FIG. 10 is a plan view of the multilayer ceramic capacitor shown in FIG. 1 , indicating the locations of the surface areas of the external electrodes.

FIG. 11 is an enlarged cross-sectional view showing the state of the e-dimension end at the surface portion of an external electrode located on the main surfaces.

FIG. 12A shows a first internal electrode pattern of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 12B shows a second internal electrode pattern of the multilayer ceramic capacitor shown in FIG. 1 .

FIG. 13 is an outside perspective view of the stacked body of the multilayer ceramic capacitor in FIG. 1 .

FIG. 14 is an outside perspective view of a product obtained by forming main-surface undercoating electrode layers on the stacked body in FIG. 13 .

FIG. 15 is a plan view showing the state in which a sputtering mask used in manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention is aligned with the stacked body.

FIG. 16 is an outside perspective view of a product obtained by providing lateral-surface undercoating electrode layers on the stacked body in FIG. 14 on which main-surface undercoating electrode layers have been provided.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1. Multilayer Ceramic Capacitor

A multilayer ceramic capacitor according to a first preferred embodiment of the present invention will now be described. FIG. 1 is an outside perspective view showing a first preferred embodiment of a multilayer ceramic capacitor according to the present invention. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1 . FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1 . FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 1 . FIG. 5 is an exploded perspective view of the stacked body shown in FIGS. 1 to 4 . FIGS. 6, 7 and 8 are respectively a plan view, a front view, and a right side view of the multilayer ceramic capacitor shown in FIG. 1 .

A multilayer ceramic capacitor 10 includes a rectangular or substantially rectangular parallelepiped stacked body 12 and external electrodes 14, 15.

Stacked body 12 includes a plurality of dielectric layers 16 and a plurality of internal electrodes 18. Stacked body 12 includes a first main surface 12 a and a second main surface 12 b opposite to each other in stacking direction x, a first lateral surface 12 c and a second lateral surface 12 d opposite to each other in longitudinal direction y orthogonal or substantially orthogonal to stacking direction x, and a third lateral surface 12 e and a fourth lateral surface 12 f opposite to each other in width direction z orthogonal or substantially orthogonal to stacking direction x and longitudinal direction y. Each of first and second main surfaces 12 a and 12 b extends along longitudinal direction y and width direction z. Each of first and second lateral surfaces 12 c and 12 d extends along stacking direction x and width direction z. Each of third and fourth lateral surfaces 12 e and 12 f extends along stacking direction x and longitudinal direction y. Thus, stacking direction x is the direction connecting first and second main surfaces 12 a and 12 b, longitudinal direction y is the direction connecting first and second lateral surfaces 12 c and 12 d, and width direction z is the direction connecting third and fourth lateral surfaces 12 e and 12 f.

The corners and ridge lines of stacked body 12 are preferably rounded. Each corner refers to an intersection of three planes of stacked body 12, and each ridge line refers to an intersection of two planes of stacked body 12.

Dielectric layers 16 include outer layer portions 16 a and an effective layer portion 16 b. Outer layer portions 16 a are located adjacent to first and second main surfaces 12 a and 12 b of stacked body 12. Specifically, one of the outer layer portions 16 a is the dielectric layer 16 located between first main surface 12 a and one of internal electrodes 18 that is closest to first main surface 12 a, and the other of the outer layer portions 16 a is the dielectric layer 16 located between second main surface 12 b and one of internal electrodes 18 that is closest to second main surface 12 b. Each of outer layer portions 16 a preferably has a thickness of not less than about 3 μm and not more than about 12 μm, for example. Effective layer portion 16 b is the region sandwiched between both outer layer portions 16 a. That is, effective layer portion 16 b is the region in which internal electrodes 18 are stacked.

As shown in FIG. 9 , where the dimension of stacked body 12 in stacking direction x is denoted by t, and the dimension of effective layer portion 16 b in stacking direction x is denoted by t′, the ratio of dimension t′ of effective layer portion 16 b in stacking direction x to dimension t of stacked body 12 in stacking direction x preferably satisfies not less than about 53% and not more than about 83%, for example. Dimension t of stacked body 12 in stacking direction x is preferably not less than about 30 μm and not more than about 80 μm, for example. Further, the ratio of the total thickness of both outer layer portions 16 a to dimension t′ of effective layer portion 16 b in stacking direction x is preferably not less than about 21% and not more than about 88%, for example. The ratio of the total thickness of both outer layer portions 16 a to dimension t of stacked body 12 in stacking direction x is preferably not less than about 18% and not more than about 47%, for example.

Dielectric layers 16 may be made of, for example, dielectric material. Examples of dielectric materials include dielectric ceramic that includes barium titanate, calcium titanate, strontium titanate, barium calcium titanate, or calcium zirconate, as a primary component. If any of the above-listed dielectric materials is contained as a primary component, secondary components, less in content than the primary component, may be added in accordance with the desired characteristics of multilayer ceramic capacitor 10. Examples of the secondary components include Mg compounds, Mn compounds, Si compounds, Al compounds, V compounds, Ni compounds, and rare-earth compounds.

The average thickness of dielectric layers 16 sandwiched between internal electrodes 18 is preferably, for example, not less than about 0.4 μm and not more than about 1.0 μm, more preferably not less than about 0.4 μm and not more than about 0.8 μm, and still more preferably not less than about 0.4 μm and not more than about 0.6 μm.

In multilayer ceramic capacitor 10, as shown in FIGS. 2 to 5 , internal electrodes 18 are alternately stacked, with dielectric layers 16 being interposed therebetween in stacked body 12.

Stacked body 12 includes a plurality of first internal electrodes 18 a and a plurality of second internal electrodes 18 b, as a plurality of internal electrodes 18. First internal electrodes 18 a and second internal electrodes 18 b are alternately stacked, with dielectric layers 16 being interposed therebetween.

First internal electrodes 18 a are disposed on the surfaces of dielectric layers 16. First internal electrodes 18 a include first facing portions 20 a facing first and second main surfaces 12 a and 12 b. First internal electrodes 18 a are stacked in the direction connecting first and second main surfaces 12 a and 12 b.

Second internal electrodes 18 b are disposed on the surfaces of dielectric layers 16 other than dielectric layers 16 on which first internal electrodes 18 a are disposed. Second internal electrodes 18 b include second facing portions 20 b facing first and second main surfaces 12 a and 12 b. Second internal electrodes 18 b are stacked in the direction connecting first and second main surfaces 12 a and 12 b.

First internal electrodes 18 a include first leading portions 22 a leading to first and third lateral surfaces 12 c and 12 e of stacked body 12, and second leading portions 22 b leading to second and fourth lateral surfaces 12 d and 12 f of stacked body 12. Thus, first leading portions 22 a are exposed at first and third lateral surfaces 12 c and 12 e of stacked body 12, and second leading portions 22 b are exposed at second and fourth lateral surfaces 12 d and 12 f of stacked body 12. First leading portions 22 a exposed at first and third lateral surfaces 12 c and 12 e of stacked body 12, and second leading portions 22 b exposed at second and fourth lateral surfaces 12 d and 12 f of stacked body 12 are preferably not less than about 135 μm and not more than about 195 μm, for example, in dimension in longitudinal direction y and width direction z. First leading portions 22 a and second leading portions 22 b preferably have a rectangular or substantially rectangular shape.

Second internal electrodes 18 b include third leading portions 24 a leading to first and fourth lateral surfaces 12 c and 12 f of stacked body 12, and fourth leading portions 24 b leading to second and third lateral surfaces 12 d and 12 e of stacked body 12. Thus, third leading portions 24 a are exposed at first and fourth lateral surfaces 12 c and 12 f of stacked body 12, and fourth leading portions 24 b are exposed at second and third lateral surfaces 12 d and 12 e of stacked body 12. Third leading portions 24 a exposed at first and fourth lateral surfaces 12 c and 12 f of stacked body 12, and fourth leading portions 24 b exposed at second and third lateral surfaces 12 d and 12 e of stacked body 12 are preferably not less than about 135 μm and not more than about 195 μm, for example, in dimension in longitudinal direction y and width direction z. Third leading portions 24 a and fourth leading portions 24 b preferably have a rectangular or substantially rectangular shape.

When multilayer ceramic capacitor 10 is seen in stacking direction x, the straight lines connecting first leading portions 22 a and second leading portions 22 b of first internal electrodes 18 a intersect with the straight lines connecting third leading portions 24 a and fourth leading portions 24 b of second internal electrodes 18 b.

Stacked body 12 includes lateral portions (L gaps) 26 a of stacked body 12 defined by one end of first facing portions 20 a in longitudinal direction y and first lateral surface 12 c, and defined by the other end of second facing portions 20 b in longitudinal direction y and second lateral surface 12 d. The average dimension of lateral portions (L gaps) 26 a of stacked body in longitudinal direction y is preferably, for example, not less than about 10 μm and not more than about 70 μm, more preferably not less than about 10 μm and not more than about 50 μm, and still more preferably not less than about 10 μm and not more than about 30 μm.

Further, stacked body 12 includes lateral portions (W gaps) 26 b of stacked body 12 defined by one end of first facing portions 20 a in width direction z and third lateral surface 12 e, and defined by the other end of second facing portions 20 b in width direction z and fourth lateral surface 12 f. The average dimension of lateral portions (W gaps) 26 b of stacked body 12 in width direction z is preferably, for example, not less than about 10 μm and not more than about 70 μm, more preferably not less than about 10 μm and not more than about 50 μm, still more preferably not less than about 10 μm and not more than about 30 μm.

Examples of the materials of internal electrodes 18 include a metal, such as Ni, Cu, Ag, Pd, or Au, or an alloy including one of these metals, such as an Ag—Pd alloy. Internal electrodes 18 may further include dielectric particles having the same composition as the ceramic included in dielectric layers 16. The number of stacked internal electrodes 18 is preferably not less than about 20 and not more than about 80, for example. The average thickness of internal electrodes 18 is preferably, for example, not less than about 0.3 μm and not more than about 1.0 μm, and more preferably not less than about 0.6 μm and not more than about 1.0 μm.

On first and second lateral surfaces 12 c and 12 d of stacked body 12, external electrodes 14, 15 are provided.

External electrodes 14 include a first external electrode 14 a electrically connected to first leading portions 22 a of first internal electrodes 18 a, and a second external electrode 14 b electrically connected to second leading portions 22 b.

First external electrode 14 a covers first leading portions 22 a exposed at first and third lateral surfaces 12 c and 12 e, and covers a portion of each of first main surface 12 a, second main surface 12 b, first lateral surface 12 c, and third lateral surface 12 e. Second external electrode 14 b covers second leading portions 22 b exposed at second and fourth lateral surfaces 12 d and 12 f, and covers a portion of each of first main surface 12 a, second main surface 12 b, second lateral surface 12 d, and fourth lateral surface 12 f. First external electrode 14 a and second external electrode 14 b preferably have a rectangular or substantially rectangular shape on each of main surfaces 12 a, 12 b.

External electrodes 15 include a third external electrode 15 a electrically connected to third leading portions 24 a of second internal electrodes 18 b, and a fourth external electrode 15 b electrically connected to fourth leading portions 24 b.

Third external electrode 15 a covers third leading portions 24 a exposed at first and fourth lateral surfaces 12 c and 12 f, and covers a portion of each of first main surface 12 a, second main surface 12 b, first lateral surface 12 c, and fourth lateral surface 12 f. Fourth external electrode 15 b covers fourth leading portions 24 b exposed at second and third lateral surfaces 12 d and 12 e, and covers a portion of each of first main surface 12 a, second main surface 12 b, second lateral surface 12 d, and third lateral surface 12 e. Third external electrode 15 a and fourth external electrode 15 b preferably have a rectangular or substantially rectangular shape on each of main surfaces 12 a, 12 b.

Curved portions are provided at the corners of external electrodes 14, 15 located at the ridge lines at the boundaries between first and second main surfaces 12 a and 12 b and lateral surfaces 12 c, 12 d, 12 e, 12 f; and at the corners of external electrodes 14, 15 located on first and second main surfaces 12 a and 12 b. Specifically, as shown in FIG. 6 , curved portions 14 a ₁, 14 a ₂ are provided at the corners of first external electrode 14 a located at the ridge lines at the boundaries between first and second main surfaces 12 a, 12 b and lateral surfaces 12 c, 12 e; and curved portions 14 a ₃ are provided at the corners of first external electrode 14 a located on first and second main surfaces 12 a and 12 b. Curved portions 14 b ₁, 14 b ₂ are provided at the corners of second external electrode 14 b located at the ridge lines at the boundaries between first and second main surfaces 12 a, 12 b and lateral surfaces 12 d, 12 f; and curved portions 14 b ₃ are provided at the corners of second external electrode 14 b located on first and second main surfaces 12 a and 12 b. Curved portions 15 a ₁, 15 a ₂ are provided at the corners of third external electrode 15 a located at the ridge lines at the boundaries between first and second main surfaces 12 a, 12 b and lateral surfaces 12 c, 12 f; and curved portions 15 a ₃ are provided at the corners of third external electrode 15 a located on first and second main surfaces 12 a and 12 b. Curved portions 15 b ₁, 15 b ₂ are provided at the corners of fourth external electrode 15 b located at the boundaries between first and second main surfaces 12 a, 12 b and lateral surfaces 12 d, 12 e; and curved portions 15 b 3 are provided at the corners of fourth external electrode 15 b located on first and second main surfaces 12 a and 12 b.

In stacked body 12, first facing portions 20 a and second facing portions 20 b face each other, with dielectric layers 16 being interposed therebetween, thus causing electrical properties (e.g., capacitance). This provides a capacitance between first and second external electrodes 14 a, 14 b, to which first internal electrodes 18 a are connected, and third and fourth external electrodes 15 a and 15 b, to which second internal electrodes 18 b are connected. With such structure, multilayer ceramic capacitor 10 defines a capacitor.

Each external electrode 14, 15 preferably includes an undercoating electrode layer 28 and a plating layer 30 in this order from the stacked body 12 side. Each undercoating electrode layer 28 includes a main-surface undercoating electrode layer 32 and a lateral-surface undercoating electrode layer 34.

Main-surface undercoating electrode layers 32 are formed on first and second main surfaces 12 a and 12 b by sputtering, for example, to define sputtered electrodes. Main-surface undercoating electrode layers 32, formed as sputtered electrodes, preferably include Ni, Cr, and Cu, for example. The thickness of the sputtered electrodes in stacking direction x is preferably, for example, not less than about 50 nm and not more than about 400 nm, and more preferably not less than about 50 nm and not more than about 130 nm. Main-surface undercoating electrode layers 32 on first and second main surfaces 12 a and 12 b may be baked electrode layers. In this case, main-surface undercoating electrode layers 32 are formed by, for example, screen printing with an external electrode paste including, for example, Ni as a primary component. The thickness of the baked electrode layers on the main surfaces in stacking direction x is preferably not less than about 1 μm and not more than about 5 μm, for example.

Lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of first and third lateral surfaces 12 c and 12 e and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers first leading portions 22 a of first internal electrodes 18 a exposed at first and third lateral surfaces 12 c and 12 e of stacked body 12, and also covers main-surface undercoating electrode layers 32. Thus, undercoating electrode layer 28 for first external electrode 14 a is formed. Also, lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of first and fourth lateral surfaces 12 c and 12 f and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers third leading portions 24 a of second internal electrodes 18 b exposed at first and fourth lateral surfaces 12 c and 12 f of stacked body 12. Thus, undercoating electrode layer 28 for third external electrode 15 a is formed.

In the same or substantially the same manner, lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of second and fourth lateral surfaces 12 d and 12 f and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers second leading portions 22 b of first internal electrodes 18 a exposed at second and fourth lateral surfaces 12 d and 12 f of stacked body 12. Thus, undercoating electrode layer 28 for second external electrode 14 b is formed. Also, lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of second and third lateral surfaces 12 d and 12 e and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers fourth leading portions 24 b of second internal electrodes 18 b exposed at second and third lateral surfaces 12 d and 12 e of stacked body 12. Thus, undercoating electrode layer 28 for fourth external electrode 15 b is formed.

Plating layer 30 preferably includes, for example, at least one selected from the group consisting of Ni, Sn, Cu, Ag, Pd, Ag—Pd alloy, and Au. Plating layer 30 may include a plurality of layers. If the multilayer ceramic capacitor is to be mounted on a substrate surface, plating layer 30 preferably has a double-layer structure including a Ni plating layer and a Sn plating layer. The Ni plating layer can prevent undercoating electrode layer 28 from being eroded by solder when multilayer ceramic capacitor 10 is mounted. The Sn plating layer improves the solder wettability when multilayer ceramic capacitor 10 is mounted, thus allowing easy mounting. A Cu plating layer may be interposed between undercoating electrode layer 28 and the Ni plating layer. If the multilayer ceramic capacitor is to be embedded into a substrate, plating layer 30 preferably has a single-layer structure including a Cu plating layer.

The average thickness of the Ni plating layer is preferably not less than about 2 μm and not more than about 4 μm, for example. The average thickness of the Sn plating layer is preferably not less than about 2 μm and not more than about 4 μm, for example. The average thickness of the Cu plating layer is preferably not less than about 5 μm and not more than about 8 μm, for example.

The dimension of multilayer ceramic capacitor 10 in longitudinal direction y is referred to as dimension L. The dimension of multilayer ceramic capacitor 10 in stacking direction x, including stacked body 12 and external electrodes 14, 15, is referred to as dimension T. The dimension of multilayer ceramic capacitor 10 in width direction z, including stacked body 12 and external electrodes 14, 15, is referred to as dimension W.

When dimension L of multilayer ceramic capacitor 10 in longitudinal direction y is compared with dimension W in width direction z, about 0.85≤W/L≤about 1, and L≤about 750 μm, for example, are preferably satisfied. If dimension L is larger than this, the flexural strength will decrease.

Dimension T of multilayer ceramic capacitor 10 in stacking direction x preferably satisfies, for example, about 50 μm≤T≤about 110 μm. Dimension T being less than about 50 μm is not preferred because it would increase the warpage of the stacked body at the time of firing and thus reduce the flexural strength. Dimension T being more than about 110 μm is not preferred as a thin multilayer ceramic capacitor.

The edges defining first, second, third, and fourth external electrodes 14 a, 14 b, 15 a, and 15 b located on first or second main surface 12 a or 12 b of stacked body 12 are preferably parallel or substantially parallel to the long edges of stacked body 12.

As shown in FIGS. 6 and 7 , w₁>e_(r) is preferably satisfied, where w₁ denotes the maximum dimension of external electrodes 14, located on first and second main surfaces 12 a and 12 b in longitudinal direction y or width direction z, and e_(r) denotes the dimension of external electrodes 14, 15 located at the ridge lines at the boundaries between first or second main surface 12 a or 12 b and lateral surfaces 12 c, 12 d, 12 e, 12 f.

As shown in FIGS. 6 and 7 , w₁≥w₂ is preferably satisfied, where w₁ denotes the maximum dimension of external electrodes 14, located on first and second main surfaces 12 a and 12 b in longitudinal direction y or width direction z, and w₂ denotes the dimension of external electrodes 14, 15 located on first, second, third, and fourth lateral surfaces 12 c, 12 d, 12 e, and 12 f in longitudinal direction y or width direction z.

As shown in FIGS. 7 and 8 , the ratio of the shortest of the dimensions g_(r) and g_(c) (g-dimension) to dimension 1 or w is preferably not less than about 17% and not more than about 50%, for example, where g_(r) denotes the dimension of a portion between adjacent external electrodes 14 and 15, at the ridge lines at the boundaries between the main surfaces and lateral surfaces; g_(c) denotes the dimension of stacked body 12 at the ½ position (i.e., the center) in the stacking direction, between adjacent external electrodes 14 and 15; 1 denotes the dimension of stacked body 12 in longitudinal direction y; and w denotes the dimension of stacked body 12 in width direction z.

As shown in FIGS. 7 and 8 , the ratio of e_(r) to dimension 1 or w (e_(r)/1 or e_(r)/w) is preferably not less than about 25% and not more than about 45%, for example, where e_(r) denotes the dimension of external electrodes 14, 15 located at the ridge lines at the boundaries between the main surfaces and lateral surfaces, 1 denotes the dimension of stacked body 12 in longitudinal direction y, and w denotes the dimension of stacked body 12 in width direction z.

As shown in FIG. 9 , d₃≤d₂≤d₁ is preferably satisfied, where d₁ denotes the thickness of external electrodes 14, 15 in longitudinal direction y or width direction z in the same plane as internal electrode 18 located closest to first or second main surface 12 a or 12 b; d₂ denotes the thickness of external electrodes 14, 15 in stacking direction x, at the ½ position in longitudinal direction y or width direction z, located on first or second main surface 12 a or 12 b; and d₃ denotes the thickness of external electrodes 14, 15 in longitudinal direction y or width direction z, at the ½ position in stacking direction x, located on first, second, third, and fourth lateral surfaces 12 c, 12 d, 12 e, and 12 f.

As shown in FIG. 10 , the ratio of min [A₁, A₂, A₃, A₄] to max [A₁, A₂, A₃, A₄] is preferably, for example, not less than about 36% and not more than about 100%, and more preferably not more than about 90%, where A₁, A₂, A₃, and A₄ respectively denote the surface areas of first, second, third, and fourth external electrodes 14 a, 14 b, 15 a, and 15 b that are located on first or second main surface 12 a or 12 b of stacked body 12.

Assuming that each of dimensions 1 and w of stacked body 12 is about 600 μm, each of surface areas A₁, A₂, A₃, and A₄ of respective first, second, third, and fourth external electrodes 14 a, 14 b, 15 a, and 15 b that are located on first or second main surface 12 a or 12 b of stacked body 12 is preferably not less than about 22500 μm² and not more than about 62500 μm², for example.

Further, assuming that each of dimensions 1 and w of stacked body 12 is about 600 μm, and that the surface portions of first, second, third, and fourth external electrodes 14 a, 14 b, 15 a, and 15 b located on first or second main surface 12 a or 12 b of stacked body 12 are translated and superimposed on one another, the area that does not overlap is preferably, for example, not less than about 0 μm² and not more than about 40000 μm², and more preferably not less than about 4000 μm².

As shown in FIG. 10 , the ratio of surface area A₁′ to surface area A₁ of first external electrode 14 a, the ratio of surface area A₂′ to surface area A₂ of second external electrode 14 b, the ratio of surface area A₃′ to surface area A₃ of third external electrode 15 a, and the ratio of surface area A₄′ to surface area A₄ of fourth external electrode 15 b are each preferably, for example, not less than about 75%, where surface area A₁′ is the surface area of a region having a height of about 5 μm or less from the maximum height of bumps on the surface portion of first external electrode 14 a located on first or second main surface 12 a or 12 b, surface area A₂′ is the surface area of a region having a height of about 5 μm or less from the maximum height of bumps on the surface portion of second external electrode 14 b located on first or second main surface 12 a or 12 b, surface area A₃′ is the surface area of a region having a height of about 5 μm or less from the maximum height of bumps on the surface portion of third external electrode 15 a located on first or second main surface 12 a or 12 b, and surface area A₄′ is the surface area of a region having a height of about 5 μm or less from the maximum height of bumps on the surface portion of fourth external electrode 15 b located on first or second main surface 12 a or 12 b.

Further, as shown in FIG. 11 , angle θ formed by the surface of stacked body 12 and straight line 12 is preferably not less than about 8° and not more than about 37°, for example, where P₁ denotes the intersection point between the inclined edge that defines the e-dimension end of external electrode 14, 15, and straight line l₁ that is parallel to the surface of stacked body and that passes through the maximum height of bumps on the surface part of external electrode 14, 15 located on first or second main surface 12 a or 12 b; P₂ denotes the e-dimension end of external electrode 14, 15; and l₂ denotes the straight line connecting intersection point P₁ and e-dimension end P₂.

In multilayer ceramic capacitor 10 shown in FIG. 1 , where the dimension of stacked body 12 in stacking direction x is denoted by t, and the dimension of effective layer portion 16 b in stacking direction x is denoted by t′, the ratio of dimension t′ of effective layer portion 16 b in stacking direction x to dimension t of stacked body 12 in stacking direction x preferably satisfies not less than about 53% and not more than about 83%, for example. This provides multilayer ceramic capacitor 10 with a reduced thickness and including external electrodes reliably provided thereon by plating deposition.

Further, in multilayer ceramic capacitor 10 shown in FIG. 1 , dimension t of stacked body 12 in stacking direction x may preferably be, for example, not less than about 30 μm and not more than about 80 μm. This provides multilayer ceramic capacitor 10 including external electrodes further reliably provided thereon by plating deposition.

Further, in multilayer ceramic capacitor 10 shown in FIG. 1 , first leading portions 22 a exposed at first and third lateral surfaces 12 c and 12 e of stacked body 12, and second leading portions 22 b exposed at second and fourth lateral surfaces 12 d and 12 f of stacked body 12 may preferably be, for example, not less than about 135 μm and not more than about 195 μm in dimension in longitudinal direction y and width direction z. Also, third leading portions 24 a exposed at first and fourth lateral surfaces 12 c and 12 f of stacked body 12, and fourth leading portions 24 b exposed at second and third lateral surfaces 12 d and 12 e of stacked body 12 may preferably be, for example, not less than about 135 μm and not more than about 195 μm in dimension in longitudinal direction y and width direction z. This provides multilayer ceramic capacitor 10 including external electrodes reliably formed thereon by plating deposition.

In multilayer ceramic capacitor 10 shown in FIG. 1 , the ratio of the total thickness of both outer layer portions 16 a to dimension t′ of effective layer portion 16 b in stacking direction x may preferably be, for example, not less than about 21% and not more than about 88%. This provides multilayer ceramic capacitor 10 including external electrodes further reliably provided thereon by plating deposition.

Further, the ratio of the total thickness of both outer layer portions 16 a to dimension t of stacked body 12 in stacking direction x may preferably be, for example, not less than about 18% and not more than about 47%. This provides multilayer ceramic capacitor 10 including external electrodes further reliably provided thereon by plating deposition.

Further, in multilayer ceramic capacitor 10 shown in FIG. 1 , first internal electrodes 18 a include first leading portions 22 a leading to first and third lateral surfaces 12 c and 12 e of stacked body 12, and second leading portions 22 b leading to second and fourth lateral surfaces 12 d and 12 f of stacked body 12. Also, second internal electrodes 18 b include third leading portions 24 a leading to first and fourth lateral surfaces 12 c and 12 f of stacked body 12, and fourth leading portions 24 b leading to second and third lateral surfaces 12 d and 12 e of stacked body 12. Accordingly, when a voltage is applied, the currents flowing through the leading portions are directed in opposite directions. This advantageously reduces the equivalent series inductance (ESL), which is a parasitic component of the multilayer ceramic capacitor.

2. Method for Manufacturing Multilayer Ceramic Capacitor

A non-limiting example of a method for manufacturing multilayer ceramic capacitor 10 will now be described.

First, ceramic green sheets and a conductive paste for internal electrodes are prepared. The ceramic green sheets and the conductive paste for internal electrodes include binders (e.g., known organic binders) and solvents (e.g., organic solvents).

Next, the ceramic green sheets are printed with the conductive paste in a predetermined pattern by, for example, gravure printing, to form internal electrode patterns as shown in FIGS. 12A and 12B. Specifically, the ceramic green sheets are applied with a paste including conductive material by gravure printing for example, thus producing conductive paste layers. The paste including conductive material is preferably, for example, metallic powder with an organic binder and an organic solvent added thereto. Ceramic green sheets with no internal electrode pattern are also produced for external layers.

Using the ceramic green sheets with internal electrode pattern, stacked sheets are produced. Specifically, stacked sheets are produced by laying a ceramic green sheet with no internal electrode pattern; then alternately laying thereon ceramic green sheets with the internal electrode pattern corresponding to first internal electrodes 18 a as shown in FIG. 12A, and ceramic green sheets with the internal electrode pattern corresponding to second internal electrodes 18 b as shown in FIG. 12B; and further laying thereon a ceramic green sheet with no internal electrode pattern. Then, the stacked sheets are pressure-bonded in stacking direction x by, for example, isostatic press, to thus produce a stacked body block.

Further, the stacked sheets are pressed in the stacking direction by, for example, isostatic press, thus producing a multilayer block.

Then, the multilayer block is cut into pieces having a predetermined size, thus producing multilayer chips. At this time, the corners and ridge lines of each multilayer chip may be rounded by barrel polishing, for example.

Next, the multilayer chip is fired, thus producing stacked body 12 as shown in FIG. 13 . The firing temperature is preferably not less than about 900° C. and not more than about 1300° C., for example, though depending on the materials of the ceramic and internal electrodes.

At this time, as shown in FIG. 13 , first leading portions 22 a of first internal electrodes 18 a are exposed at first and third lateral surfaces 12 c and 12 e of stacked body 12, and second leading portions 22 b of first internal electrodes 18 a are exposed at second and fourth lateral surfaces 12 d and 12 f of stacked body 12. In the same or substantially the same manner, third leading portions 24 a of second internal electrodes 18 b are exposed at first and fourth lateral surfaces 12 c and 12 f of stacked body 12, and fourth leading portions 24 b of second internal electrodes 18 b are exposed at second and third lateral surfaces 12 d and 12 e of stacked body 12.

Then, external electrodes 14, 15 are formed on stacked body 12. Specifically, as shown in FIG. 14 , main-surface undercoating electrode layer 32, including a Ni—Cu alloy as a primary component, is formed by sputtering on each of first and second main surfaces 12 a and 12 b, to form lateral-surface undercoating electrode layer 34 that will cover first leading portions 22 a of first internal electrodes 18 a. Also, main-surface undercoating electrode layer 32, including a Ni—Cu alloy as a primary component, is formed by sputtering on each of first and second main surfaces 12 a and 12 b, to form lateral-surface undercoating electrode layer 34 that will cover third leading portions 24 a of second internal electrodes 18 b. At this time, little or none of the material extends around the lateral surfaces.

In the same or substantially the same manner, main-surface undercoating electrode layer 32, including a Ni—Cu alloy as a primary component, is formed by sputtering on each of first and second main surfaces 12 a and 12 b, to form lateral-surface undercoating electrode layer 34 that will cover second leading portions 22 b of first internal electrodes 18 a. Also, main-surface undercoating electrode layer 32, including a Ni—Cu alloy as a primary component, is formed by sputtering on each of first and second main surfaces 12 a and 12 b, to form lateral-surface undercoating electrode layer 34 that will cover fourth leading portions 24 b of second internal electrodes 18 b. At this time, little or none of the material extends around the lateral surfaces.

In order to form main-surface undercoating electrode layers 32 by sputtering, a sputtering mask 40 as shown in FIG. 15 is used. Sputtering mask 40 includes four aperture patterns 42 to form main-surface undercoating electrode layers 32. Sputtering mask 40 is slightly larger than the outer shape of stacked body 12. Sputtering mask 40 is positioned so that the corners of stacked body 12 are exposed through respective aperture patterns 42 of sputtering mask 40 placed on the upper side of stacked body 12.

Each aperture pattern 42 preferably has a hexagonal shape. Sputtering mask 40 is placed on stacked body 12 so that, in each aperture pattern 42, opposite edges 42 a and 42 b are parallel or substantially parallel to width direction z of stacked body 12, opposite edges 42 c and 42 d are parallel or substantially parallel to longitudinal direction y of stacked body 12, and opposite edges 42 e and edge 42 f are parallel or substantially parallel to the diagonal direction of stacked body 12.

Then, as shown in FIG. 16 , lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of first and third lateral surfaces 12 c and 12 e and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers first leading portions 22 a of first internal electrodes 18 a exposed at first and third lateral surfaces 12 c and 12 e of stacked body 12, and also covers main-surface undercoating electrode layers 32. Thus, undercoating electrode layer 28 for first external electrode 14 a is formed. Also, lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of first and fourth lateral surfaces 12 c and 12 f and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers third leading portions 24 a of second internal electrodes 18 b exposed at first and fourth lateral surfaces 12 c and 12 f of stacked body 12. Thus, undercoating electrode layer 28 for third external electrode 15 a is formed.

In the same or substantially the same manner, lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of second and fourth lateral surfaces 12 d and 12 f and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers second leading portions 22 b of first internal electrodes 18 a exposed at second and fourth lateral surfaces 12 d and 12 f of stacked body 12. Thus, undercoating electrode layer 28 for second external electrode 14 b is formed. Also, lateral-surface undercoating electrode layer 34 is formed as a plated electrode by, for example, Cu plating, continuous with a portion of second and third lateral surfaces 12 d and 12 e and a portion of first and second main surfaces 12 a and 12 b, so that lateral-surface undercoating electrode layer 34 covers fourth leading portions 24 b of second internal electrodes 18 b exposed at second and third lateral surfaces 12 d and 12 e of stacked body 12. Thus, undercoating electrode layer 28 for fourth external electrode 15 b is formed.

Then, plating layer 30 is formed to cover the surface of each lateral-surface undercoating electrode layer 34. At this time, for example, a Cu plating layer, a Ni plating layer, and a Sn plating layer are formed in sequence, thus producing plating layer 30. The process of forming each plating layer may be performed a plurality of times.

Thus, multilayer ceramic capacitor 10 as shown in FIG. 1 is manufactured.

The advantageous effects of the multilayer ceramic capacitor produced in the above-described manner will be apparent from the following experimental examples.

3. Experimental Examples

The following describes example experiments conducted by the inventor of preferred embodiments of the present invention for the purpose of confirming the magnitude relationship between the stacking-direction thicknesses of the effective layer portion, the outer layer portions, and the stacked body of the multilayer ceramic capacitor in the present invention, and confirming the formation state of the external electrodes.

As experimental examples, samples of multilayer ceramic capacitors were produced in accordance with the method for manufacturing multilayer ceramic capacitors described in the above preferred embodiment.

Common specifications of the multilayer ceramic capacitors in the experimental examples were as follows.

-   -   Material of dielectric layers:

Primary component: Barium titanate

Secondary components: Mg, V, Dy, Si

-   -   Material of internal electrodes: Ni     -   Configuration of external electrodes:

Rectangular electrodes were provided on each main surface

As shown in FIG. 9 , the dimension of stacked body 12 in stacking direction x is denoted by t, and the dimension of effective layer portion 16 b in stacking direction x is denoted by t′.

In the experimental examples, samples as shown in Table 1 were prepared. In the samples of sample numbers 1 and 2, the thickness (t) of stacked body 12 in stacking direction x was both about 30 μm, and the thickness of each outer layer portion was about 12 μm and about 7 μm, respectively. In the samples of sample numbers 3 to 5, the thickness (t) of stacked body 12 in stacking direction x was all about 57 μm, and the thickness of each outer layer portion was about 12 μm, about 10 μm and about 7 μm, respectively. In the samples of sample numbers 6 and 7, the thickness (t) of stacked body 12 in stacking direction x was both about 80 μm, and the thickness of each outer layer portion was about 12 μm and about 7 μm, respectively. For each prepared sample, a thickness of each outer layer portion necessary for the thickness (t) of stacked body 12 in stacking direction x is shown.

For each sample, the ratio of dimension t′ of effective layer portion 16 b in stacking direction x to dimension t of stacked body 12 in stacking direction x, the ratio of the total thickness of both outer layer portions 16 a to dimension t′ of effective layer portion 16 b in stacking direction x, and the ratio of the total thickness of both outer layer portions 16 a to dimension t of stacked body 12 in stacking direction x were calculated. The results are shown in table 1.

TABLE 1 SPECIMEN NUMBER 1 2 3 4 5 6 7 DIMENSION OF STACKED BODY: t 30 30 57 57 57 80 80 (μm) THICKNESS OF EFFECTIVE LAYER PORTION: t′ (μm) 6 16 33 37 43 56 66 THICKNESS OF OUTER LAYER PORTION 12 7 12 10 7 12 7 (μm) RATIO OF t′ TO t 20 53 58 65 75 70 83 (%) RATIO OF TOTAL THICKNESS OF BOTH OUTER LAYER 400 88 73 54 33 43 21 PORTIONS TO THICKNESS OF EFFECTIVE LAYER PORTION (%) RATIO OF TOTAL THICKNESS OF BOTH OUTER LAYER 80 47 42 35 25 30 18 PORTIONS TO DIMENSION t OF STACKED BODY (%)

According to Table 1, with sample number 1, although external electrodes 14, 15 covered a portion of lateral surfaces 12 c, 12 d, 12 e, 12 f, it would be difficult to ensure a desired capacitance because the total thickness of both outer layer portions 16 a was as much as four times larger than dimension t′ of effective layer portion 16 b in stacking direction x.

On the other hand, with sample numbers 2 to 7, the ratio of dimension t′ of effective layer portion 16 b in stacking direction x to dimension t of stacked body 12 in stacking direction x was not less than about 53% and not more than about 83%. With any of these samples, external electrodes 14, 15 can cover a portion of lateral surfaces 12 c, 12 d, 12 e, 12 f, ensuring a desired capacitance. Also, with sample numbers 2 to 7, the ratio of the total thickness of both outer layer portions 16 a to dimension t′ of effective layer portion 16 b in stacking direction x was not less than about 21% and not more than about 88%. With any of these samples, external electrodes 14, 15 can reliably cover a portion of lateral surfaces 12 c, 12 d, 12 e, 12 f, ensuring a desired capacitance. Further, with sample numbers 2 to 7, the ratio of the total thickness of both outer layer portions 16 a to dimension t of stacked body 12 in stacking direction x was not less than about 18% and not more than about 47%. With any of these samples, external electrodes 14, 15 can more reliably cover a portion of lateral surfaces 12 c, 12 d, 12 e, 12 f, ensuring a desired capacitance.

While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims. 

What is claimed is:
 1. A multilayer ceramic capacitor comprising: a stacked body including a plurality of dielectric layers and a plurality of internal electrodes that are stacked in a stacking direction, the stacked body including: a first main surface and a second main surface opposite to each other in the stacking direction; a first lateral surface and a second lateral surface opposite to each other in a longitudinal direction orthogonal or substantially orthogonal to the stacking direction; and a third lateral surface and a fourth lateral surface opposite to each other in a width direction orthogonal or substantially orthogonal to the stacking direction and the longitudinal direction; and a plurality of external electrodes disposed on the lateral surfaces of the stacked body; wherein the plurality of internal electrodes include a plurality of first internal electrodes and a plurality of second internal electrodes alternately stacked, with the plurality of dielectric layers interposed therebetween; the plurality of first internal electrodes include: first leading portions extending to the first and third lateral surfaces; and second leading portions extending to the second and fourth lateral surfaces; the plurality of second internal electrodes include: third leading portions extending to the first and fourth lateral surfaces; and fourth leading portions extending to the second and third lateral surfaces; the plurality of external electrodes include: a first external electrode connected to the first leading portions and covering the first leading portions exposed at the first and third lateral surfaces, the first external electrode covering a portion of each of the first main surface, the second main surface, the first lateral surface, and the third lateral surface; a second external electrode connected to the second leading portions and covering the second leading portions exposed at the second and fourth lateral surfaces, the second external electrode covering a portion of each of the first main surface, the second main surface, the second lateral surface, and the fourth lateral surface; a third external electrode connected to the third leading portions and covering the third leading portions exposed at the first and fourth lateral surfaces, the third external electrode covering a portion of each of the first main surface, the second main surface, the first lateral surface, and the fourth lateral surface; and a fourth external electrode connected to the fourth leading portions and covering the fourth leading portions exposed at the second and third lateral surfaces, the fourth external electrode covering a portion of each of the first main surface, the second main surface, the second lateral surface, and the third lateral surface; about 0.85≤W/L≤about 1 is satisfied, where L denotes a dimension of the multilayer ceramic capacitor in the longitudinal direction, and W denotes a dimension of the multilayer ceramic capacitor in the width direction; the plurality of dielectric layers include outer layer portions and an effective layer portion; one of the outer layer portions is located adjacent to the first main surface of the stacked body, and another of the outer layer portions is located adjacent to the second main surface of the stacked body; the one of the outer layer portions is one of the plurality of dielectric layers that is located between the first main surface and one of the plurality of internal electrodes that is closest to the first main surface; the another of the outer layer portions is one of the plurality of dielectric layers that is located between the second main surface and one of the plurality of internal electrodes that is closest to the second main surface; the effective layer portion is a region sandwiched between the outer layer portions; and where a dimension of the stacked body in the stacking direction is denoted by t, and a dimension of the effective layer portion in the stacking direction is denoted by t′, a ratio of the dimension t′ of the effective layer portion in the stacking direction to the dimension t of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.
 2. The multilayer ceramic capacitor according to claim 1, wherein the dimension t of the stacked body in the stacking direction is not less than about 30 μm and not more than about 80 μm.
 3. The multilayer ceramic capacitor according to claim 1, wherein the first leading portions exposed at the first and third lateral surfaces of the stacked body, and the second leading portions exposed at the second and fourth lateral surfaces of the stacked body are not less than about 135 μm and not more than about 195 μm in dimension in the longitudinal direction and the width direction; and the third leading portions exposed at the first and fourth lateral surfaces of the stacked body, and the fourth leading portions exposed at the second and third lateral surfaces of the stacked body are not less than about 135 μm and not more than about 195 μm in dimension in the longitudinal direction and the width direction.
 4. The multilayer ceramic capacitor according to claim 1, wherein each of the outer layer portions is not more than about 12 μm in thickness in the stacking direction.
 5. The multilayer ceramic capacitor according to claim 1, wherein a ratio of a total thickness of both of the outer layer portions to the dimension of the effective layer portion in the stacking direction is not less than about 21% and not more than about 88%.
 6. The multilayer ceramic capacitor according to claim 1, wherein a ratio of a total thickness of both of the outer layer portions to the dimension of the stacked body in the stacking direction is not less than about 18% and not more than about 47%.
 7. The multilayer ceramic capacitor according to claim 1, wherein corners and ridge lines of the stacked body are rounded.
 8. The multilayer ceramic capacitor according to claim 4, wherein a dimension of each of the outer layer portions is not less than about 3 μm.
 9. The multilayer ceramic capacitor according to claim 1, wherein the plurality dielectric layers are made of a dielectric ceramic including barium titanate, calcium titanate, strontium titanate, barium calcium titanate, or calcium zirconate, as a primary component.
 10. The multilayer ceramic capacitor according to claim 9, wherein the dielectric ceramic further includes at least one of Mg compounds, Mn compounds, Si compounds, Al compounds, V compounds, Ni compounds, and rare-earth compounds as a secondary component.
 11. The multilayer ceramic capacitor according to claim 1, wherein an average thickness of each the plurality of dielectric layers is not less than about 0.4 μm and not more than about 1.0 μm.
 12. The multilayer ceramic capacitor according to claim 1, wherein an average thickness of each the plurality of dielectric layers is not less than about 0.4 μm and not more than about 0.8 μm.
 13. The multilayer ceramic capacitor according to claim 1, wherein an average thickness of each the plurality of dielectric layers is not less than about 0.4 μm and not more than about 0.6 μm.
 14. The multilayer ceramic capacitor according to claim 1, wherein the plurality of first internal electrodes include first facing portions facing the first and second main surfaces; and the plurality of second internal electrodes include second facing portions facing the first and second main surfaces.
 15. The multilayer ceramic capacitor according to claim 14, wherein the stacked body includes a first lateral portion defined by one end of the first facing portions in the longitudinal direction and the first lateral surface, and a second lateral portion defined by another end of the second facing portions in longitudinal direction and the second lateral surface.
 16. The multilayer ceramic capacitor according to claim 15, wherein an average dimension of the first and second lateral portions of the stacked body is not less than about 10 μm and not more than about 70 μm.
 17. The multilayer ceramic capacitor according to claim 15, wherein an average dimension of the first and second lateral portions of the stacked body is not less than about 10 μm and not more than about 50 μm.
 18. The multilayer ceramic capacitor according to claim 15, wherein an average dimension of the first and second lateral portions of the stacked body is not less than about 10 μm and not more than about 30 μm. 